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高少谷 教授

高少谷/Shao-Ku Kao
副教授/Professor 
Department of Electrical Engineering 
Chang Gung University, Taiwan 
電話/TEL:03-2118800-3198
信箱/Email:
kaosk@mail.cgu.edu.tw
研究領域/專長: 醫電與VLSI領域/Phase locked loops (PLLs) Delay locked loops (DLLs)Duty cycle corrector (DCC)

  

Biography

Shao-Ku Kao received the M.S. in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2002 and the Ph.D. degree in electronics engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2007.
He is currently an Assistant Professor in the department of electrical engineering, Chang Gung University of Taiwan. His research interests include phase locked loops, delay locked loops, duty cycle corrector circuit and mixed-mode clock generator.

 

Publication List

Journal Papers:

[1]Shao-Ku Kao, Yu-Zhang Lee, Chun-Yu Ku, Hsiang-Chi Cheng,”Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor,” Microelectronics Journal, vol.56, pp.134-141, Oct. 2016.

[2] Shao-Ku Kao, Hsiang-Chi Cheng and Jian-Da Lin,” A self-calibrated delay-locked loop with low static phase error,” International Journal of Circuit Theory and Applications, Vol 44, pp. 929-944, Apr., 2016

[3]Shao-Ku Kao and Sheng-Hung Hsueh, “A fast-corrected all-digital DCC with synchronous input clock”, International Journal of Circuit Theory and Applications, Vol 43, pp. 1845–1860, Dec., 2015

[4]Shao-KuKao, Jen-HouWu, and Hsiang-Chi Cheng, "All-digital controlled boost DC-DC converter with all-digital DLL-based calibration", Microelectronics Journal, vol.46, pp.970-980, Oct. 2015.

[5]Shao-Ku Kao, Hsiang-Chi Cheng, and Yong-De You, " Pulsewidth control loop with a frequency detector for wide frequency range operation ", Microelectronics Journal, vol.46, pp. 291-297, Apr. 2015.

[6]Shao-Ku Kao, Yong-De You,.” Pulsewidth control loop with low control voltage ripple” e, International Journal of  Electronics Letters, 1:4, 168-178, DOI: 10.1080/21681724.2013.85837208 Nov 2013.

[7] Shao-Ku Kao, Fu-Jen Hsieh (2013): A fast-locking PLL with all-digital lockedaid circuit, International Journal of   Electronics, 100:2, 245-258,01 Jun 2012

[8] Shao-Ku Kao, Bo-Jiun Chen, and Shen-Iuan Liu, " A 62.5-625MHz Anti-reset All-digital Delay-locked Loop ", IEEE Trans. Circuits and Systems- II: Express Briefs, vol.54, July 2007.

[9] Shao-Ku Kao and Shen-Iuan Liu, "All-digital Fast-locked Synchronous Duty Cycle Corrector",IEEE Trans. Circuits and Systems- II: Express Briefs, vol.53, Dec. 2006.

[10] Shao-Ku Kao, Shen-Iuan Liu,”All-Digital Clock Deskew Buffer with Variable Duty cycles”, IEICE Trans Electron, vol. 89-C, June 2006

[11] You-Jen Wang, Shao-Ku Kao, and Shen-Iuan Liu,“All-Digital Delay-Locked Loop/Pulsewidth-Control Loop With Adjustable Duty Cycles,”IEEE J. Solid-State Circuits, vol. 41, June 2006.

Conference Papers:

[1]Bo-Jiun Chen, Shao-Ku Kao, Shen-Juan Liu,” An All-digital Duty Cycle Corrector”,VLSI Design, Automation and Test, 2006 International Symposium on, April 2006

  

 

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