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魏一勤 副教授

魏一勤/I-Chyn Wey
副教授/Associate Professor 
Department of Electrical Engineering 
Chang Gung University, Taiwan 
電話/TEL:886-3-2118800-5327
信箱/Email:icwey@mail.cgu.edu.tw
研究領域/專長:醫電與VLSI領域/VLSI電路設計,低功率電路設計,生醫積體電路設計,物聯網感測訊號處理積體電路設計,抗雜訊電路設計
Lab: 超大型積體電路實驗室 

 

Biography

I-Chyn Wey (魏一勤) received the B.S. and the M.S. degree from the Department of Electronics Engineering, Chang-Gung University (CGU), Taoyuan, Taiwan, in 2001 and 2003, respectively, and the Ph. D. degree from the Graduate Institute of Electronics Engineering, National Taiwan University (NTU), Taipei, Taiwan, in 2008.
Since Aug. 2008, he joined the faculty of Department of Electrical Engineering, Chang Gung University, Taoyuan, Taiwan, where he is currently an Assistant Professor. His research interests are in noise-tolerant circuits design, VLSI circuits design, VLSI/DSP design, low power VLSI design, and communication-inspired VLSI design.

 

Publication List

Journal Papers:

1.      Yan Li, Yufeng Li, I-Chyn Wey, Jianhao Hu, Fan Yang , Xuan Zeng , Xiaoxue Jiang, and Jie Chen, (2018, Aug.) Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 8, AUGUST 2018. SCI. IF=4.075.

2.    Bing-Chen Wu, I-Chyn Wey (2017, Jul). Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 1-13.

3.    Xiaojian Yu, Kambiz Moez, I-Chyn Wey, Mohamad Sawan, Jie Chen (2016 Aug.) A Fully-Integrated Multistage Cross-Coupled Voltage Multiplier with No Reversion Power Loss in Standard CMOS Process. IEEE TCAS-II.

4.    I-Chyn Wey, Jia-Wei Zhang (2015, Nov). An H-Tree Simplified Markov-Random-Field Noise-Tolerant Circuit Design. International Journal of Electronics.

5.    I-Chyn Wey, Bing-Chen Wu, Chien-Chang Peng, Cihun-Siyong Alex Gong, Chang-Hong Yu (2015, Apr). Robust C-element design for soft-error mitigation. IEICE Electronics Express.

6.    Cihun-Siyong Alex Gong, Yu-Lin Tsou, Yan-Hsien Yang, Hwann-Kaeo Chiou, I-Chyn Wey, Meng-Tsan Tsai, Changhong Yu, and Lingling Lin (2015, Mar). Design and implementation of a voltage-controlled oscillator for MICS-based sensor network system. International Journal of Microwave and Wireless Technologies.

7.    Xin-Xiang Lian, I-Chyn Wey, Chien-Chang Peng, Zhi-Qun Cheng (2015, Feb). Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications. IEICE Electronics Express.

8.    I-Chyn Wey, Chien-Chang Peng, and Feng-Yu Liao (2015, Jan). Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS.

9.    Lili Lin, I-Chyn Wey, Jing-Hua Ding (2014, Nov). Fast Predictive Motion Estimation Algorithm with Adaptive Search Mode Based on Motion Type Classification. Signal, Image and Video Processing.

10. I-Chyn Wey, Chien-Chang Peng, Hen-Jui Chou, Po-Tsang Chen (2014, May). Reliable and low error dual modular redundancy FIR filter with wide protection window. IEICE Electronics Express.

11. I-Chyn Wey, Chun-Wei Chang, Yu-Cheng Liao, and Heng-Jui Chou (2014, Jan). Noise-Tolerant Dynamic CMOS Circuits Design by Using True Single-Phase Clock Latching Technique. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS.

12. I-Chyn Wey, Ye-Jhih Shen (2014, Jan). Hardware-Efficient Common-Feedback Markov-Random-Field Probabilistic-based Noise-Tolerant VLSI Circuits. Integration, the VLSI Journal. NSC 99-2221-E-182-063.

13. I-Chyn Wey, Yu-Sheng Yang, Bin-Cheng Wu, Chien-Chang Peng (2014, Jan). A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design. MICROELECTRONICS JOURNAL.

14. I-Chyn Wey, Yi-Jung Lan, Chien-Chang Peng (2013, Jun). Reliable ultra-lowvoltage low-power probabilistic-based noise-tolerant latch design. MICROELECTRONICS RELIABILITY, 53(12), 2057–2069.

15. I-Chyn Wey, Tz-Cheng He, Hwang-Cherng Chow, Pie-Hsien Sun, Chien-Chang Peng (2013, Feb). A high-speed, high fan-in dynamic comparator with low transistor count. INTERNATIONAL JOURNAL OF ELECTRONICS.

16. I-Chyn Wey, Shu-Hao Kuo2 (2013, Jan). All digital folded low-area, low-power maximum power point tracking chip for photovoltaic energy conversion system. International Journal of Circuit Theory and Applications.

17. I-Chyn Wey and Chun-Chien Wang (2012, Oct). Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(10), 1923 -1928.

18. I-Chyn Wey, Chien-Chang Peng, and Hwang-Cherng Chow (2012, Oct). Wide bandwidth and high precision power supply noise detector by using dual peak detection sample and hold circuits. International Journal of Circuit Theory and Applications.

 

Conference Papers:

1.    I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, and An-Yeu (Andy) Wu, “A 2Gb/s High-Speed Scalable Shift-Register Based On-Chip Serial Communication Design for SoC Applications,” in Proc. of 2005 IEEE International Symposium on Circuits and Systems(ISCAS 2005), Kobe, Japan, pp. 1074-1077, May 2005.

2.   Chia-Tsun Wu, Wei Wang, I-Chyn Wey, and An-Yeu (Andy) Wu, “A Scalable DCO Design for Portable ADPLL Designs,” in Proc. of 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan, pp. 5449-5452, May 2005.

3.    I-Chyn Wey, You-Gang Chen, Chia-Tsun Wu, Wei Wang, and An-Yeu (Andy) Wu, “A High-Speed Scalable Shift-Register Based On-Chip Serial Communication Design for SoC Applications,” in Proc. of 2005 IEEE Ph.D. Research in Microelectronics and Electronics (PRIME 2005), Lausanne, Switzerland, July 2005.

4.    Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu (Andy) Wu, “A Frequency Estimation Algorithm for ADPLL Designs with Two-Cycle Lock-in Time,” in Proc. of 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006), Kos Island, Greece, pp. 4082-4085, May 2006.

5.    Wei Wang, I-Chyn Wey, Chia-Tsun Wu, and An-Yeu (Andy) Wu, “A Portable All-Digital Pulsewidth Control Loop for SOC Applications”, in Proc. of 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006), Kos Island, Greece, pp. 3165-3168, May 2006.

6.    I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen and An-Yeu (Andy) Wu,“0.18μm Probabilistic-Based Noise-Tolerate Circuit Design and Implementation with 28.7dB Noise-Immunity Improvement”, in Proc. of IEEE Asian Solid-State Circuits Conference (A-SSCC 2006), Hangzhou, China, pp. 291-294, Nov. 2006.

7.    You-Gang Chen, I-Chyn Wey, and An-Yeu (Andy) Wu, “A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment”, in Proc. of IEEE Asian Solid-State Circuits Conference (A-SSCC 2006), Hangzhou, China, pp. 295-298, Nov. 2006.

8.    Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, and An-Yeu (Andy) Wu, “Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules,” in Proc. of 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, USA, pp. 869-872, May 2007.

9.    Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu (Andy) Wu, Hong Zhao, “Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design,” in Proc. of 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, USA, pp. 1803-1806, May 2007.

10.  Woon Tiong Ang, Hui Fei Rao, Changhong Yu, Jilin Liu, I-Chyn Wey, An-Yeu (Andy) Wu, Hong Zhao, Jie Chen, “A clock-fault tolerant architecture and circuit for reliable nanoelectronics system,”In Proc. of 2007 nternational Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2007), Rabat, Morocco, pp. 186-191, Sep. 2007.

11. Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, and An-Yeu (Andy) Wu, “Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency,” in Proc. of 2007 IEEE Workshop on Signal Processing Systems (SiPS-2007), Shanghai, China, pp. 493-498, Oct. 2007.

12.  I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen and An-Yeu (Andy) Wu, “A 0.13μm Hardware-Efficient Probabilistic-Based Noise-Tolerant Circuit Design and Implementation with 24.5dB Noise-Immunity Improvement,” in Proc. of 2007 IEEE Asian Solid-State Circuits Conf. (A-SSCC-2007), Jeju, Korea, pp. 295-298, Nov. 2007.

13.  Huifei Rao, Jie Chen, Vicky H. Zhao, Woon Tiong Ang, I-Chyn Wey and An-Yeu (Andy) Wu, “An Efficient Methodology to Evaluate Nanoscale Circuit Fault-tolerance Performance based on Belief Propagation,” accepted by 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, USA, May 2007.

14. I-Chyn Wey and Chun-Chien Wang, “Low-error and Area-efficient Fixed-width Multiplier by Using Minor Input Correction Vector,” in Porc. of IEEE International Conference on Electronics and Information Engineering, Kyoto, Japan, Aug. 2010.

15. I-Chyn Wey, Chien-Chang Peng, Yu-Jiang Liao, and Yu-Sheng Yang, “A Precise Power Supply Noise Detector with High-Linearity,” in Proc. of Workshop on Design, Analysis and Tools for Integrated Circuits and Systems, Hong-Kong, China, Mar. 2011.

16.  I-Chyn Wey, Cheng-Chen Ho, Yi-Sheng Lin, and Chien-Chang Peng, “An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term”, IMECS, Hong-Kong, China, March 2012.

17 I-Chyn Wey, Chien-Chang Peng, Wan-Rong Wu, Chao-Chyun Chen, and Chi-Nan Chuang, “High-Performance Noise-Tolerant Markov Random Field Circuit Based on Transmission-Gate Design”, ITC-CSCC, Hokaido, Japan, July 2012.

18. I-Chyn Wey, Chien-Chang Peng 'A Wide-Range Self-Checking Power Supply Noise Detection Circuit,' Bali, Indonisia, ICEIC 2013.
19. I-Chyn Wey, Zhe-Yu Lin, Yu-Jie Tian, Sheng-Hong Yu, Pin-Si Lin,'Low-Voltage Low-Power Pipelined Input Subsampled Replica
Algorithmic Noise-Tolerant Motion Estimation Circuit Design', Singapore, International Symposium on Computer, Communication,
Control and Automation, 2013.
20. I-Chyn Wey, Po-Jen Lin, Bing-Chen Wu, and Chien-Chang Peng, and Pin-Si Lin,'Near-Threshold-Voltage Circuit Design: The Design
Challenges and Chances,' Jeju, Korea, ISOCC 2014. 21. Lian xinXiang, Chen Chao-chyun, Wey I-Chyn, Cheng Zhi-Qun,'The
Discrete-Time Model of the Small Signal Compensator of the Buck Converte,' Beijin, China, 2014.
22. I-Chyn Wey, 'Low Delay Variance Near-Threshold-Voltage CMOS Circuits Design by Using Multi-Path Combinations', ICMCEI,
Fujian,China, 2015.
23. I-Chyn Wey, “Low-power Design towards Implantable Neural Signal Processor- Energy Efficiency Analysis for Near-Threshold Voltage Circuits Design”, Beijin, China, ISBB 2015.

Patents:

1.    Jie Chen, I-Chyn Wey, Chang-Hong Yu, “Ultra Low Power and Noise Tolerant Circuit Design Methodology,” (Submitting) US, 2007.11.

 

 

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